The present invention relates to a task processing apparatus in a multi-CPU system constituted by a plurality of CPUs designed to respectively execute different tasks.
As a conventional task processing apparatus of this type, a card encoder like the one shown in FIG. 4 is available. This card encoder is constituted by a personal computer 1, a main CPU 2, a communication CPU 3, and a card convey system 4. The card encoder serves to record value information on a magnetic card 5. The card convey system 4 for actually conveying the card 5, recording value information thereon, and issuing the card having the value information recorded thereon is constituted by a card loading section 41, a recording/reproducing section 42, and a selector section 43. A sub-CPU 41A, a pair of sub-CPUs 42A and 42B, and a sub-CPU 43A are respectively arranged for these sections.
When an operator performs a card issue operation by using the personal computer 1, a card issue command signal 10 is sent from the personal computer 1 to the main CPU 2. Upon reception of the card issue command signal 10, the main CPU 2 gives a load command to the sub-CPU 41A of the card loading section 41 via the communication CPU 3 to load the card 5 on which no information is recorded. As a result, one card 5 is loaded by the card loading section 41, and the sub-CPU 41A determines that information can be recorded on the card 5. Information indicating this determination is transmitted to the main CPU 2 via the communication CPU 3. The main CPU 2 then supplies a record command to the sub-CPU 42A of the recording/reproducing section 42 via the communication CPU 3 to record value information on the card 5. Upon reception of information indicating the completion of recording from the sub-CPU 42A which has recorded the value information on the card 5, the main CPU 2 supplies reproduction and check commands to the sub-CPU 42B of the recording/reproducing section 42 via the communication CPU 3 to reproduce and check the information recorded on the card 5.
Upon reception of a check result from the sub-CPU 42B via the communication CPU 3, which result is obtained by checking the recorded/reproduced information in accordance with these commands, the main CPU 2 transmits defect/non-defect information of the card 5 corresponding to the check result to the sub-CPU 43A of the selector section 43 via the communication CPU 3, thus causing the sub-CPU 43A to select a card on which value information is properly recorded. Upon completion of selection of the card 5, the sub-CPU 43A transmits a response signal 11 corresponding to the card issue command signal 10 to the personal computer 1. When such processing is repeated for each card 5, and a predetermined number of cards 5 are issued, the card issue processing is completed.
When, for example, the conventional card encoder as a task processing apparatus is to issue the card 5, the main CPU 2 transmits information to the sub-CPUs 41A, 42A, 42B, and 43A for respectively executing different tasks, e.g., recording of value information and card selection processing with respect to the card 5, via the communication CPU 3, thereby directly controlling the sub-CPUs. For this reason, the load on the main CPU 2 increases to cause a delay in the processing performed by the main CPU 2. In addition, since the communication CPU 3 is required to transmit information between the main CPU 2 and the sub-CPUs 41A, 42A, 42B, and 43A, the apparatus cannot be economically designed.